Attribute is the DC resistance, which then determines voltage drop and power dissipation and possibly even influences the 3D current distribution. Instead of entering nets and components individually, this allows us to model the path of current from plus to minus with lower effort and in a more physically correct way. In the end, we get the temperature distribution generated by the power dissipation of the currents and components, taking into account the copper distribution in the layout.
An application is the control of a 3-phase DC motor. Texas Instruments provides a good ALTIUM data set for testing the method : DRV8305-Q1EVM. The input voltage range of the board is specified as 4.4 to 45V which is ideally suited to the automotive application. The maximum current that can be supplied to the motor is limited to 25A.
In the model we focus on the power stage with the associated MOSFETs and the shunt resistors for current measurement. For real applications it would be necessary to select the motor and program the control accordingly. Since the maximum input current is limited to 25A, a maximum output current of 6.7 A per phase is specified in order not to overload the board. This means that 20 A flow from VBAT back to GND through the inductor, the mosfets, the shunts and the copper of the PCB. The transistors have RDS(on)=3.3 mOhm (max.) each and the shunts 5 mOhm each. The heat dissipation of other components (e.g. drivers) is intentionally not considered. For the current flow in the power stage are relevant: 6 MOSFETs, 3+1 shunts and 1 inductor.
The TI evaluation board DRV8305-Q1 is made of 4 layers and is simulated with TRM3.4 in free convection in 20 °C ambient air under laboratory conditions.
The colored display of the potential field makes it easy to detect a bottleneck in the copper and thus, in combination with the evaluations of the current density, to identify possible weak points in the area of the PDN (power distributed network). For power stages, the optimized routing of the power supply is a must, otherwise unnecessary losses on the PCB can occur, which can cause local overloads.
The starting point of the current is the DC input connector with VBAT. The end point is at the same connector and has the designation GND. High and low transistors of the half bridges are flooded in RMS approximation. The higher the current density, the higher the local power dissipation. Conductor routing as well as the used surfaces for current transport of the Eval kit are well designed. Furthermore, with regard to electro-migration, the current density remains below 200A/mm² in local hotspots.
The partitioning of Joule heat to the individual layers is:
Depending on the position and neighborhood, the components have different temperatures. Because of the environmental condition « free standing in the lab » it is not critical here. Note the asymmetric heating of the electrolytic capacitors. The positioning of the electrolytic capacitors is electrically optimized, but thermally it has to be considered as critical, because they are heated by the transistors and therefore the lifetime is reduced.